1. Field of the Invention
This invention relates to a plasma display panel driving method and system, and more particularly to a plasma display panel driving method and system which ensures achievement of writing at high response speed to provide a display.
2. Description of the Prior Art
As is well-known in the art, in a plasma display panel (hereinafter referred to as a PDP), electrodes covered with dielectric layers are disposed opposite to each other with a discharge gas space defined therebetween. In the case of providing a display by discharge between the electrodes supplied with an alternating sustain voltages, a write pulse is impressed to selected ones of the electrodes in such a manner as to exceed a firing voltage.
As shown in FIG. 1, there is formed between electrodes X and Y an equivalent circuit in which capacitances Ct of the dielectric layers and that Cw of a cell defined between the electrodes X and Y are connected in series with one another. Where a sustain voltage Vs such, for example, as depicted in FIG. 2 is previously impressed to the electrodes X and Y and a write pulse V.sub.w is impressed thereto while superimposed on the peak of the sustain voltage V.sub.S, the resulting amplitude value exceeds a firing voltage V.sub.F to cause ionization of a gas sealed in a cell between the electrodes X and Y, thus producing a discharge.
By the discharge, a wall charge is stored in either one of the dielectric layer according to the polarity of the impressed voltage to provide a wall voltage V.sub.Q. With the wall voltage V.sub.Q, the voltage applied to the cell becomes such that V.sub.W -V.sub.F and it becomes lower than the firing voltage V.sub.F, thus stopping the discharge.
The wall voltage V.sub.Q remains for a certain period of time because the wall charge stored in the dielectric layer is not rapidly extinguished even after the write pulse V.sub.W and the sustain voltage V.sub.S have been reduced to zero. Namely, once a discharge is produced by writing, it is stored in the form of a wall charge.
In the next half cycle of the sustain voltage V.sub.S, a discharge is caused again when the potential difference between the wall voltage V.sub.Q and the sustain voltage V.sub.S exceeds the firing voltage V.sub.F and, in this case, the polarity of the wall voltage V.sub.Q is reversed. Namely, discharge is repeatedly produced at every half cycle of the sustain voltage V.sub.S to provide a display.
In the case of erasing the display thus provided, an erasing pulse V.sub.E is impressed when the value of the sustain voltage V.sub.S is relatively low and the potential difference between it and the wall voltage V.sub.Q is far smaller than the firing voltage V.sub.F. The erasing pulse V.sub.E is selected to be of such an amplitude value that the difference between the superimposed value of the erasing pulse V.sub.E and the sustain voltage V.sub.S, and the wall voltage V.sub.Q is a little greater than the firing voltage V.sub.F. With the erasing pulse V.sub.E, the cell is discharged but no wall voltage of opposite polarity is thereby generated, so that no discharge is produced by the sustain voltage applied after a half cycle.
With such a PDP, a memory display is possible and its erasing is freely controllable. However, its operation is mainly dependent on the gas discharge, and hence has an operation time lag characteristic due to a firing time T f and a statistical time lag Ts determined by the number of electrons initially ionizing the gas and causing avalanche until a steady space charge distribution by discharge is formed after the impression of the write pulse V.sub.w, as is the case with a typical usual discharge tube. The time lag Ts is usually greater than the firing time Tf. For example, where the generation of initial electrons by light excitation is limited by disposing the PDP in a dark place or where the PDP is not used for a long time, the operation lag time increases and no discharge is produced by applying one write pulse only and, in some cases, no discharge is generated unless the write voltage is impressed for a period of several milliseconds to several seconds. Thus, the time lag Ts is very large, as compared with the firing time Tf which is about 1.mu.sec., so that the time lag is likely to cause an erroneous display.